clock_generator/firmware
finga 0395da78de Generate default clock signals
The "demo" from Adafruits Si5351 library is used to produce a working
proof of concept which sets PLLA to 720MHz, PLLB to 705MHz and then
Multisynth0, Multisynth1 and Multisynth2 to 120MHz, 12MHz and 13.56MHz
respectively.
2021-09-27 21:29:11 +02:00
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src Generate default clock signals 2021-09-27 21:29:11 +02:00