Generate default clock signals
The "demo" from Adafruits Si5351 library is used to produce a working proof of concept which sets PLLA to 720MHz, PLLB to 705MHz and then Multisynth0, Multisynth1 and Multisynth2 to 120MHz, 12MHz and 13.56MHz respectively.
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@ -24,6 +24,9 @@
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#define SI5351_ADDRESS 0x60
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#define SI5351_REGISTER_3_OUTPUT_ENABLE_CONTROL 3
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#define SI5351_REGISTER_177_PLL_RESET 177
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#define SYM_ENTRY(SYM) { SYM, sizeof(SYM) / 2 }
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static uint8_t EEMEM eeprom_contrast = 8;
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@ -171,6 +174,69 @@ static volatile uint8_t enc = 0;
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static volatile uint8_t value_contrast;
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static volatile uint8_t value_backlight;
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static const uint8_t m_si5351_regs_15to92_149to170[100][2] = {
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// Init
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{3, 0xFF},
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{16, 0x4F}, /* CLK0 Control: 8mA drive, Multisynth 0 as CLK0 source, Clock
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not inverted, Source = PLLA, Multisynth 0 in integer mode,
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clock powered up */
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{17, 0x4F}, /* CLK1 Control: 8mA drive, Multisynth 1 as CLK1 source, Clock
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not inverted, Source = PLLA, Multisynth 1 in integer mode,
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clock powered up */
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{18, 0x6F}, /* CLK2 Control: 8mA drive, Multisynth 2 as CLK2 source, Clock
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not inverted, Source = PLLB, Multisynth 2 in integer mode,
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clock powered up */
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{19, 0x80}, /* CLK3 Control: Not used ... clock powered down */
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{20, 0x80}, /* CLK4 Control: Not used ... clock powered down */
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{21, 0x80}, /* CLK5 Control: Not used ... clock powered down */
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{22, 0x80}, /* CLK6 Control: Not used ... clock powered down */
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{23, 0x80}, /* CLK7 Control: Not used ... clock powered down */
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// PLL_A Setup (720MHz)
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{26, 0x00},
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{27, 0x05},
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{28, 0x00},
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{29, 0x0C},
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{30, 0x66},
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{31, 0x00},
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{32, 0x00},
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{33, 0x02},
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// PLL_B Setup (705MHz)
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{34, 0x02},
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{35, 0x71},
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{36, 0x00},
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{37, 0x0C},
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{38, 0x1A},
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{39, 0x00},
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{40, 0x00},
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{41, 0x86},
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// Multisynth0 Setup (120MHz)
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{42, 0x00},
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{43, 0x01},
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{44, 0x00},
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{45, 0x01},
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{46, 0x00},
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{47, 0x00},
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{48, 0x00},
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{49, 0x00},
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// Multisynth1 Setup (12MHz)
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{50, 0x00},
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{51, 0x01},
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{52, 0x00},
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{53, 0x1C},
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{54, 0x00},
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{55, 0x00},
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{56, 0x00},
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{57, 0x00},
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// Multisynth2 Setup (13.56MHz)
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{58, 0x00},
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{59, 0x01},
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{60, 0x00},
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{61, 0x18},
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{62, 0x00},
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{63, 0x00},
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{64, 0x00},
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{65, 0x00}};
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static void spi_init(void) {
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SPI_DDR |= (1 << SPI_SCK) | (1 << SPI_MOSI) | (1 << SPI_SS);
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SPI_PORT |= (1 << SPI_SS);
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@ -809,6 +875,13 @@ int main(void) {
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(void) &twi_read_register;
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(void) &twi_write_register;
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for (uint16_t i = 0; i < sizeof(m_si5351_regs_15to92_149to170) / 2; i++)
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twi_write_register(SI5351_ADDRESS, m_si5351_regs_15to92_149to170[i][0],
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m_si5351_regs_15to92_149to170[i][1]);
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twi_write_register(SI5351_ADDRESS, SI5351_REGISTER_177_PLL_RESET, 0xAC);
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twi_write_register(SI5351_ADDRESS, SI5351_REGISTER_3_OUTPUT_ENABLE_CONTROL, 0x00);
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// Enable interrupts
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sei();
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