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A clock generator (Si5351) controlled by an ATmega328p.
40 commits 1 branch 0 tags 516 KiB
Rust 99.2%
OpenSCAD 0.8%
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finga 0395da78de Generate default clock signals 
The "demo" from Adafruits Si5351 library is used to produce a working
proof of concept which sets PLLA to 720MHz, PLLB to 705MHz and then
Multisynth0, Multisynth1 and Multisynth2 to 120MHz, 12MHz and 13.56MHz
respectively.
2021-09-27 21:29:11 +02:00
firmware/src Generate default clock signals 2021-09-27 21:29:11 +02:00
.gitignore Generate a PWM signal for the display 2021-02-19 15:46:36 +01:00