From 0395da78de91576d21ecda9c3b8e61ef9ec85200 Mon Sep 17 00:00:00 2001
From: finga <finga@onders.org>
Date: Mon, 27 Sep 2021 20:01:46 +0200
Subject: [PATCH] Generate default clock signals

The "demo" from Adafruits Si5351 library is used to produce a working
proof of concept which sets PLLA to 720MHz, PLLB to 705MHz and then
Multisynth0, Multisynth1 and Multisynth2 to 120MHz, 12MHz and 13.56MHz
respectively.
---
 firmware/src/main.c | 73 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/firmware/src/main.c b/firmware/src/main.c
index cb2c868..9107b99 100644
--- a/firmware/src/main.c
+++ b/firmware/src/main.c
@@ -24,6 +24,9 @@
 
 #define SI5351_ADDRESS 0x60
 
+#define SI5351_REGISTER_3_OUTPUT_ENABLE_CONTROL 3
+#define SI5351_REGISTER_177_PLL_RESET 177
+
 #define SYM_ENTRY(SYM) { SYM, sizeof(SYM) / 2 }
 
 static uint8_t EEMEM eeprom_contrast = 8;
@@ -171,6 +174,69 @@ static volatile uint8_t enc = 0;
 static volatile uint8_t value_contrast;
 static volatile uint8_t value_backlight;
 
+static const uint8_t m_si5351_regs_15to92_149to170[100][2] = {
+    // Init
+    {3, 0xFF},
+    {16, 0x4F}, /* CLK0 Control: 8mA drive, Multisynth 0 as CLK0 source, Clock
+                   not inverted, Source = PLLA, Multisynth 0 in integer mode,
+                   clock powered up */
+    {17, 0x4F}, /* CLK1 Control: 8mA drive, Multisynth 1 as CLK1 source, Clock
+                   not inverted, Source = PLLA, Multisynth 1 in integer mode,
+                   clock powered up */
+    {18, 0x6F}, /* CLK2 Control: 8mA drive, Multisynth 2 as CLK2 source, Clock
+                   not inverted, Source = PLLB, Multisynth 2 in integer mode,
+                   clock powered up */
+    {19, 0x80}, /* CLK3 Control: Not used ... clock powered down */
+    {20, 0x80}, /* CLK4 Control: Not used ... clock powered down */
+    {21, 0x80}, /* CLK5 Control: Not used ... clock powered down */
+    {22, 0x80}, /* CLK6 Control: Not used ... clock powered down */
+    {23, 0x80}, /* CLK7 Control: Not used ... clock powered down */
+    // PLL_A Setup (720MHz)
+    {26, 0x00},
+    {27, 0x05},
+    {28, 0x00},
+    {29, 0x0C},
+    {30, 0x66},
+    {31, 0x00},
+    {32, 0x00},
+    {33, 0x02},
+    // PLL_B Setup  (705MHz)
+    {34, 0x02},
+    {35, 0x71},
+    {36, 0x00},
+    {37, 0x0C},
+    {38, 0x1A},
+    {39, 0x00},
+    {40, 0x00},
+    {41, 0x86},
+    // Multisynth0 Setup (120MHz)
+    {42, 0x00},
+    {43, 0x01},
+    {44, 0x00},
+    {45, 0x01},
+    {46, 0x00},
+    {47, 0x00},
+    {48, 0x00},
+    {49, 0x00},
+    // Multisynth1 Setup (12MHz)
+    {50, 0x00},
+    {51, 0x01},
+    {52, 0x00},
+    {53, 0x1C},
+    {54, 0x00},
+    {55, 0x00},
+    {56, 0x00},
+    {57, 0x00},
+    // Multisynth2 Setup (13.56MHz)
+    {58, 0x00},
+    {59, 0x01},
+    {60, 0x00},
+    {61, 0x18},
+    {62, 0x00},
+    {63, 0x00},
+    {64, 0x00},
+    {65, 0x00}};
+
 static void spi_init(void) {
     SPI_DDR |= (1 << SPI_SCK) | (1 << SPI_MOSI) | (1 << SPI_SS);
     SPI_PORT |= (1 << SPI_SS);
@@ -809,6 +875,13 @@ int main(void) {
     (void) &twi_read_register;
     (void) &twi_write_register;
 
+    for (uint16_t i = 0; i < sizeof(m_si5351_regs_15to92_149to170) / 2; i++)
+        twi_write_register(SI5351_ADDRESS, m_si5351_regs_15to92_149to170[i][0],
+                           m_si5351_regs_15to92_149to170[i][1]);
+
+    twi_write_register(SI5351_ADDRESS, SI5351_REGISTER_177_PLL_RESET, 0xAC);
+    twi_write_register(SI5351_ADDRESS, SI5351_REGISTER_3_OUTPUT_ENABLE_CONTROL, 0x00);
+
     // Enable interrupts
     sei();