finga/clock_generator
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

board: Add vias and raise KiCAD version
All checks were successful
ci/woodpecker/push/woodpecker Pipeline was successful
Details

Browse source 
Add vias and raise KiCAD version.
This commit is contained in:
finga 2022-04-17 01:24:22 +02:00
parent f48955974d
commit dbf5733488
10 changed files with 11574 additions and 6688 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

109
board/clock_gen-cache.lib
View file

@ -94,42 +94,6 @@ X Pin_9 9 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_USB_B_Mini
#
DEF Connector_USB_B_Mini J 0 40 Y Y 1 F N
F0 "J" -200 450 50 H V L CNN
F1 "Connector_USB_B_Mini" -200 350 50 H V L CNN
F2 "" 150 -50 50 H I C CNN
F3 "" 150 -50 50 H I C CNN
ALIAS USB_B_Mini
$FPLIST
USB*
$ENDFPLIST
DRAW
C -150 85 25 0 1 10 F
C -25 135 15 0 1 10 F
S -200 -300 200 300 0 1 10 f
S -5 -300 5 -270 0 1 0 N
S 10 50 -20 20 0 1 10 F
S 200 -205 170 -195 0 1 0 N
S 200 -105 170 -95 0 1 0 N
S 200 -5 170 5 0 1 0 N
S 200 195 170 205 0 1 0 N
P 2 0 1 10 -75 85 25 85 N
P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N
P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N
P 4 0 1 10 25 110 25 60 75 85 25 110 F
P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F
P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N
X VBUS 1 300 200 100 L 50 50 1 1 w
X D- 2 300 -100 100 L 50 50 1 1 P
X D+ 3 300 0 100 L 50 50 1 1 P
X ID 4 300 -200 100 L 50 50 1 1 P
X GND 5 0 -400 100 U 50 50 1 1 w
X Shield 6 -100 -400 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
@ -163,8 +127,8 @@ $FPLIST
$ENDFPLIST
DRAW
P 2 0 1 0 50 0 -50 0 N
P 4 0 1 8 50 50 50 -50 -50 0 50 50 N
P 6 0 1 8 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
P 6 0 1 10 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
@ -248,14 +212,33 @@ X S2 S2 300 -100 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# MCU_Microchip_ATmega_ATmega328P-PU
# clock_gen-rescue_AP2112K-3.3-Regulator_Linear
#
DEF MCU_Microchip_ATmega_ATmega328P-PU U 0 20 Y Y 1 F N
DEF clock_gen-rescue_AP2112K-3.3-Regulator_Linear U 0 10 Y Y 1 F N
F0 "U" -200 225 50 H V L CNN
F1 "clock_gen-rescue_AP2112K-3.3-Regulator_Linear" 0 225 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23-5" 0 325 50 H I C CNN
F3 "" 0 100 50 H I C CNN
$FPLIST
SOT?23?5*
$ENDFPLIST
DRAW
S -200 175 200 -200 0 1 10 f
X VIN 1 -300 100 100 R 50 50 1 1 W
X GND 2 0 -300 100 U 50 50 1 1 W
X EN 3 -300 0 100 R 50 50 1 1 I
X NC 4 300 0 100 L 50 50 1 1 N N
X VOUT 5 300 100 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# clock_gen-rescue_ATmega328P-PU-MCU_Microchip_ATmega
#
DEF clock_gen-rescue_ATmega328P-PU-MCU_Microchip_ATmega U 0 20 Y Y 1 F N
F0 "U" -500 1450 50 H V L BNN
F1 "MCU_Microchip_ATmega_ATmega328P-PU" 100 -1450 50 H V L TNN
F1 "clock_gen-rescue_ATmega328P-PU-MCU_Microchip_ATmega" 100 -1450 50 H V L TNN
F2 "Package_DIP:DIP-28_W7.62mm" 0 0 50 H I C CIN
F3 "" 0 0 50 H I C CNN
ALIAS ATmega48P-20PU ATmega48A-PU ATmega48PA-PU ATmega88PV-10PU ATmega88P-20PU ATmega88A-PU ATmega88PA-PU ATmega168PV-10PU ATmega168P-20PU ATmega168A-PU ATmega168PA-PU ATmega328-PU ATmega328P-PU
$FPLIST
DIP*W7.62mm*
$ENDFPLIST
@ -292,24 +275,38 @@ X XTAL1/PB6 9 600 600 100 L 50 50 1 1 T
ENDDRAW
ENDDEF
#
# Regulator_Linear_AP2112K-3.3
# clock_gen-rescue_USB_B_Mini-Connector
#
DEF Regulator_Linear_AP2112K-3.3 U 0 10 Y Y 1 F N
F0 "U" -200 225 50 H V L CNN
F1 "Regulator_Linear_AP2112K-3.3" 0 225 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23-5" 0 325 50 H I C CNN
F3 "" 0 100 50 H I C CNN
ALIAS AP2204K-1.8 AP2204K-2.5 AP2204K-2.8 AP2204K-3.0 AP2204K-3.3 AP2204K-5.0 AP2127K-1.0 AP2127K-1.2 AP2127K-1.5 AP2127K-1.8 AP2127K-2.5 AP2127K-2.8 AP2127K-3.0 AP2127K-3.3 AP2127K-4.2 AP2127K-4.75 AP2112K-1.2 AP2112K-1.8 AP2112K-2.5 AP2112K-2.6 AP2112K-3.3
DEF clock_gen-rescue_USB_B_Mini-Connector J 0 40 Y Y 1 F N
F0 "J" -200 450 50 H V L CNN
F1 "clock_gen-rescue_USB_B_Mini-Connector" -200 350 50 H V L CNN
F2 "" 150 -50 50 H I C CNN
F3 "" 150 -50 50 H I C CNN
$FPLIST
SOT?23?5*
USB*
$ENDFPLIST
DRAW
S -200 175 200 -200 0 1 10 f
X VIN 1 -300 100 100 R 50 50 1 1 W
X GND 2 0 -300 100 U 50 50 1 1 W
X EN 3 -300 0 100 R 50 50 1 1 I
X NC 4 300 0 100 L 50 50 1 1 N N
X VOUT 5 300 100 100 L 50 50 1 1 w
C -150 85 25 0 1 10 F
C -25 135 15 0 1 10 F
S -200 -300 200 300 0 1 10 f
S -5 -300 5 -270 0 1 0 N
S 10 50 -20 20 0 1 10 F
S 200 -205 170 -195 0 1 0 N
S 200 -105 170 -95 0 1 0 N
S 200 -5 170 5 0 1 0 N
S 200 195 170 205 0 1 0 N
P 2 0 1 10 -75 85 25 85 N
P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N
P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N
P 4 0 1 10 25 110 25 60 75 85 25 110 F
P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F
P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N
X VBUS 1 300 200 100 L 50 50 1 1 w
X D- 2 300 -100 100 L 50 50 1 1 P
X D+ 3 300 0 100 L 50 50 1 1 P
X ID 4 300 -200 100 L 50 50 1 1 P
X GND 5 0 -400 100 U 50 50 1 1 w
X Shield 6 -100 -400 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#

3
board/clock_gen-rescue.dcm Normal file
View file

@ -0,0 +1,3 @@
EESchema-DOCLIB Version 2.0
#
#End Doc Library

102
board/clock_gen-rescue.lib Normal file
View file

@ -0,0 +1,102 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# AP2112K-3.3-Regulator_Linear
#
DEF AP2112K-3.3-Regulator_Linear U 0 10 Y Y 1 F N
F0 "U" -200 225 50 H V L CNN
F1 "AP2112K-3.3-Regulator_Linear" 0 225 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23-5" 0 325 50 H I C CNN
F3 "" 0 100 50 H I C CNN
$FPLIST
SOT?23?5*
$ENDFPLIST
DRAW
S -200 175 200 -200 0 1 10 f
X VIN 1 -300 100 100 R 50 50 1 1 W
X GND 2 0 -300 100 U 50 50 1 1 W
X EN 3 -300 0 100 R 50 50 1 1 I
X NC 4 300 0 100 L 50 50 1 1 N N
X VOUT 5 300 100 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# ATmega328P-PU-MCU_Microchip_ATmega
#
DEF ATmega328P-PU-MCU_Microchip_ATmega U 0 20 Y Y 1 F N
F0 "U" -500 1450 50 H V L BNN
F1 "ATmega328P-PU-MCU_Microchip_ATmega" 100 -1450 50 H V L TNN
F2 "Package_DIP:DIP-28_W7.62mm" 0 0 50 H I C CIN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP*W7.62mm*
$ENDFPLIST
DRAW
S -500 -1400 500 1400 0 1 10 f
X ~RESET~/PC6 1 600 -300 100 L 50 50 1 1 T
X XTAL2/PB7 10 600 500 100 L 50 50 1 1 T
X PD5 11 600 -1000 100 L 50 50 1 1 T
X PD6 12 600 -1100 100 L 50 50 1 1 T
X PD7 13 600 -1200 100 L 50 50 1 1 T
X PB0 14 600 1200 100 L 50 50 1 1 T
X PB1 15 600 1100 100 L 50 50 1 1 T
X PB2 16 600 1000 100 L 50 50 1 1 T
X PB3 17 600 900 100 L 50 50 1 1 T
X PB4 18 600 800 100 L 50 50 1 1 T
X PB5 19 600 700 100 L 50 50 1 1 T
X PD0 2 600 -500 100 L 50 50 1 1 T
X AVCC 20 100 1500 100 D 50 50 1 1 W
X AREF 21 -600 1200 100 R 50 50 1 1 P
X GND 22 0 -1500 100 U 50 50 1 1 P N
X PC0 23 600 300 100 L 50 50 1 1 T
X PC1 24 600 200 100 L 50 50 1 1 T
X PC2 25 600 100 100 L 50 50 1 1 T
X PC3 26 600 0 100 L 50 50 1 1 T
X PC4 27 600 -100 100 L 50 50 1 1 T
X PC5 28 600 -200 100 L 50 50 1 1 T
X PD1 3 600 -600 100 L 50 50 1 1 T
X PD2 4 600 -700 100 L 50 50 1 1 T
X PD3 5 600 -800 100 L 50 50 1 1 T
X PD4 6 600 -900 100 L 50 50 1 1 T
X VCC 7 0 1500 100 D 50 50 1 1 W
X GND 8 0 -1500 100 U 50 50 1 1 W
X XTAL1/PB6 9 600 600 100 L 50 50 1 1 T
ENDDRAW
ENDDEF
#
# USB_B_Mini-Connector
#
DEF USB_B_Mini-Connector J 0 40 Y Y 1 F N
F0 "J" -200 450 50 H V L CNN
F1 "USB_B_Mini-Connector" -200 350 50 H V L CNN
F2 "" 150 -50 50 H I C CNN
F3 "" 150 -50 50 H I C CNN
$FPLIST
USB*
$ENDFPLIST
DRAW
C -150 85 25 0 1 10 F
C -25 135 15 0 1 10 F
S -200 -300 200 300 0 1 10 f
S -5 -300 5 -270 0 1 0 N
S 10 50 -20 20 0 1 10 F
S 200 -205 170 -195 0 1 0 N
S 200 -105 170 -95 0 1 0 N
S 200 -5 170 5 0 1 0 N
S 200 195 170 205 0 1 0 N
P 2 0 1 10 -75 85 25 85 N
P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N
P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N
P 4 0 1 10 25 110 25 60 75 85 25 110 F
P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F
P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N
X VBUS 1 300 200 100 L 50 50 1 1 w
X D- 2 300 -100 100 L 50 50 1 1 P
X D+ 3 300 0 100 L 50 50 1 1 P
X ID 4 300 -200 100 L 50 50 1 1 P
X GND 5 0 -400 100 U 50 50 1 1 w
X Shield 6 -100 -400 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

10086
board/clock_gen.kicad_pcb
View file

File diff suppressed because it is too large Load diff

75
board/clock_gen.kicad_prl Normal file
View file

@ -0,0 +1,75 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "clock_gen.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

431
board/clock_gen.kicad_pro Normal file
View file

@ -0,0 +1,431 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.15,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 2.7,
"height": 5.4,
"width": 5.4
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.09999999999999999,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"use_height_for_length_calcs": true
},
"track_widths": [
0.0,
0.5
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 1.2,
"drill": 0.6
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "clock_gen.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"pin_symbol_size": 0.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"a9d4def3-098f-4221-ba43-8fb2ededfbf7",
""
]
],
"text_variables": {}
}

3429
board/clock_gen.kicad_sch Normal file
View file

File diff suppressed because it is too large Load diff

9
board/clock_gen.sch
View file

@ -1,6 +1,5 @@
EESchema Schematic File Version 4
LIBS:clock_gen-cache
EELAYER 26 0
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
@ -15,7 +14,7 @@ Comment3 ""
Comment4 ""
$EndDescr
$Comp
L MCU_Microchip_ATmega:ATmega328P-PU U4
L clock_gen-rescue:ATmega328P-PU-MCU_Microchip_ATmega U4
U 1 1 603004D8
P 2150 5800
F 0 "U4" H 1509 5846 50 0000 R CNN
@ -60,7 +59,7 @@ ICSP
Text Notes 5450 5900 0 125 ~ 25
I2C
$Comp
L Connector:USB_B_Mini J1
L clock_gen-rescue:USB_B_Mini-Connector J1
U 1 1 610FCCC0
P 1900 1500
F 0 "J1" H 1955 1967 50 0000 C CNN
@ -384,7 +383,7 @@ Connection ~ 3550 5100
Wire Wire Line
3550 5100 3550 5400
$Comp
L Regulator_Linear:AP2112K-3.3 U1
L clock_gen-rescue:AP2112K-3.3-Regulator_Linear U1
U 1 1 6111CFDB
P 3000 1400
F 0 "U1" H 3000 1742 50 0000 C CNN

4015
board/plot/clock_gen-drl_map.ps
View file

File diff suppressed because it is too large Load diff

3
board/sym-lib-table Normal file
View file

@ -0,0 +1,3 @@
(sym_lib_table
(lib (name clock_gen-rescue)(type Legacy)(uri ${KIPRJMOD}/clock_gen-rescue.lib)(options "")(descr ""))
)