finga/clock_generator: A clock generator (Si5351) controlled by an ATmega328p.

A clock generator (Si5351) controlled by an ATmega328p.

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finga bd217ce6e7 Disable `CKDIV8` and adapt to clock div. factor Configure fuses for the `fuses` target in Makefile to disable `CKDIV8`. Adapt PWM generation in `lcd_update_backlight()` to new clock division factor, as well as interrupt handling, debouncing and dechattering. This also enables partially lower PWM frequencies (between off and former lowest PWM setting) for a dimmer lcd backlight.	2021-09-21 19:10:46 +02:00
firmware/src	Disable `CKDIV8` and adapt to clock div. factor	2021-09-21 19:10:46 +02:00
.gitignore	Generate a PWM signal for the display	2021-02-19 15:46:36 +01:00

finga bd217ce6e7 Disable CKDIV8 and adapt to clock div. factor

Configure fuses for the `fuses` target in Makefile to disable
`CKDIV8`. Adapt PWM generation in `lcd_update_backlight()` to new
clock division factor, as well as interrupt handling, debouncing and
dechattering.

This also enables partially lower PWM frequencies (between off and
former lowest PWM setting) for a dimmer lcd backlight.

2021-09-21 19:10:46 +02:00

firmware/src Disable CKDIV8 and adapt to clock div. factor 2021-09-21 19:10:46 +02:00

.gitignore Generate a PWM signal for the display 2021-02-19 15:46:36 +01:00