A clock generator (Si5351) controlled by an ATmega328p.
Find a file
finga 3f19ad6ee9
All checks were successful
ci/woodpecker/push/woodpecker Pipeline was successful
make: Set up release profile and update the readme
Due to limiting the codegen units to 1 the size of the program memory
can be reduced roughly by 10% and the data memory by a bit more than
20%.
2022-04-08 01:03:16 +02:00
board Add board files 2021-10-24 13:16:19 +02:00
firmware make: Set up release profile and update the readme 2022-04-08 01:03:16 +02:00
knob knob: Improve the design of the knob [CI SKIP] 2022-04-02 00:42:40 +02:00
.gitignore Generate a PWM signal for the display 2021-02-19 15:46:36 +01:00
.woodpecker.yml fw-rust, readme: Add CI config 2022-03-07 18:35:54 +01:00
README.md make: Set up release profile and update the readme 2022-04-08 01:03:16 +02:00

Clock Generator status-badge

The "Clock Generator" generates up to three different clock signals between 15kHz and 162MHz.

Though, the board is not limited to this, it is designed to also be usable for other applications.

Board

The board is populated with an ATmega328p, an LCD and its backlight driver, a rotary encoder which is also a push button and is powered via mini USB. The TWI port of the ATmega interfaces the Si5351 which is also driven from VCC and GND, a pin breakout for all unused pins and some more VCC and GND pins as well as an ICSP header.

The general supply voltage behind the LDO regulator is 3.3V

Note that in the PCB layout the display and the rotary encoder are placed on the backside of the PCB.

ATmega328p

The Atmega328p is programmable via the ICSP header and is the center piece of the board. All free pins can be used with J3 and the TWI with J4.

Connectors

Breakout (J3)
Pin left ATmega328p ATmega328p Pin right
1 +3.3V +3.3V 2
3 PC1 PD2 4
5 PC2 PD3 6
7 PC3 PD4 8
9 PD0 PD6 10
11 PD1 PD7 12
13 GND GND 14
TWI (J4)
Pin Signal
1 +3.3V
2 GND
3 SDA
4 SCL

Si5351

The Si5351 is capable of generating three 8kHz to 160MHz clock signals.

Internally, the Si5351 consists out of two phase locked loops which feed three parallel and independently configurable clock synthesizers.

Display

The DOGS102 graphic LCD module is controlled by SPI (Serial Peripheral Interface) and the RST (reset) and CD (control data/display data) pins. The contrast can be configured on the setup screen and its value is stored in the EEPROM (Electrically Erasable Programmable Read-Only Memory) of the ATmega.

Backlight

To drive the backlight, the Timer/Counter0 from the ATmega are used to generate a PWM (Pulse Width Modulation) signal. This enables the backlight to be variably bright. The brightness can also be configured on the setup screen, and is stored inside the EEPROM.

Rotary Encoder

To control the Clock Generator a single rotary encoder which is also a push button is used.

Firmware/Programming

Currently, there are two different implementations of the firmware. The older one which is written in C and is not finished, and the newer one which is in an early but functioning state and written in Rust.

Note that mostly due to the display, the supply voltage after the LDO regulator is 3.3V.

The Rust Firmware

To flash the firmware, connect the ICSP pins of the board to the programmer and inside the firmware/rust/ directory run cargo make --profile release all. This compiles the firmware with the release profile, burns the fuses, writes the default configuration values to the EEPROM and flashes the firmware.