finga/clock_generator
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7 commits

Author SHA1 Message Date
finga
cc105aa9c9 Enable pedantic warnings 
Enable all the warnings demanded by strict ISO C.
 2021-09-14 00:27:09 +02:00
finga
05c9888a75 Store setup settings in eeprom 
To have the values of `value_contrast` and `value_backlight` persist
over turn offs they are loaded and stored from and in the eeprom.

For preventing the flash target from earasing the eeprom the `EESAVE`
high fuse byte is set to 0 (programmed).

The values are now loaded when booted and stored when a new value is
set in the setup menu.
 2021-09-11 15:44:11 +02:00
finga
e099b0f94a Move clock speed setting into makefile 
Move clock speed setting into makefile.
 2021-09-09 20:01:23 +02:00
finga
727f89eeb0 Basic state handling 
Prepare for handling of different screens and their states and add a
minimal menu.
 2021-09-08 14:53:29 +02:00
finga
cec207984a Improve make file 
Adapt to new programmer and use variables for the clean target.
 2021-09-08 13:59:38 +02:00
finga
7f7d7b628a Interact with the display 
Enable the SPI bus to configure the display and program its ram. For
that the fastest available SPI clock is used. To configure the display
a minimal config is used which is not identical but similar to the
displays datasheet. The display can only be filled columnwise so far.
 2021-02-27 02:26:57 +01:00
finga
0065fb630f Generate a PWM signal for the display 
Generate a variable duty cycle PWM signal for the dimmable display
backlight at a frequency of 1.25kHz.

For demo und testing purposes PD5 is currently fading between 0 and
100%.
 2021-02-19 15:46:36 +01:00