finga/clock_generator
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Furbish code and comment

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Remove unneeded brackets and improve comment.
This commit is contained in:
finga 2021-09-12 01:05:33 +02:00
parent 14dd301657
commit a5d88e879c
1 changed files with 2 additions and 3 deletions
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5
firmware/src/main.c
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@ -695,10 +695,9 @@ ISR(PCINT1_vect) {
TCNT1 = 0; TCNT1 = 0;
} }
} else { // press } else { // press
if (!(TCCR1B & (1 << CS10))) { if (!(TCCR1B & (1 << CS10)))
TCCR1B |= (1 << CS11) | (1 << CS10); // Enable Timer/Counter1 TCCR1B |= (1 << CS11) | (1 << CS10); // Enable Timer/Counter1
} }
}
// TODO: proper debouncing // TODO: proper debouncing
_delay_us(70); _delay_us(70);
@ -706,7 +705,7 @@ ISR(PCINT1_vect) {
sei(); sei();
} }
// Timer/Counter1 compare match A // Timer/Counter1 compare match A for back event
ISR(TIMER1_COMPA_vect) { ISR(TIMER1_COMPA_vect) {
cli(); cli();