From 73efd9348c4b9d00a064b5c52bb5e11767e46e01 Mon Sep 17 00:00:00 2001 From: finga Date: Mon, 18 Oct 2021 16:39:20 +0200 Subject: [PATCH] First steps toward custom clocking Figuring out how to configure the clocks. --- firmware/src/main.c | 101 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 90 insertions(+), 11 deletions(-) diff --git a/firmware/src/main.c b/firmware/src/main.c index aa29b49..1f5699a 100644 --- a/firmware/src/main.c +++ b/firmware/src/main.c @@ -191,15 +191,20 @@ static const uint8_t m_si5351_regs_15to92_149to170[100][2] = { {21, 0x80}, /* CLK5 Control: Not used ... clock powered down */ {22, 0x80}, /* CLK6 Control: Not used ... clock powered down */ {23, 0x80}, /* CLK7 Control: Not used ... clock powered down */ + {24, 0x00}, /* Clock disable state 0..3 (low when disabled) */ + {25, 0x00}, /* Clock disable state 4..7 (low when disabled) */ // PLL_A Setup (720MHz) - {26, 0x00}, - {27, 0x05}, - {28, 0x00}, - {29, 0x0C}, - {30, 0x66}, - {31, 0x00}, - {32, 0x00}, - {33, 0x02}, + // P1: 0x00C66 = 3174 + // P2: 0x00002 = 2 + // P3: 0x00005 = 5 + {26, 0x00}, // D7 - D0: MSNA_P3 [15:8] + {27, 0x05}, // D7 - D0: MSNA_P3 [7:0] + {28, 0x00}, // D1 - D0: MSNA_P1 [17:16] + {29, 0x0C}, // D7 - D0: MSNA_P1 [15:8] + {30, 0x66}, // D7 - D0: MSNA_P1 [7:0] + {31, 0x00}, // D7 - D4: MSNA_P3 [19:16], D3 - D0: MSNA_P2 [19:16] + {32, 0x00}, // D7 - D0: MSNA_P2 [15:8] + {33, 0x02}, // D7 - D0: MSNA_P2 [7:0] // PLL_B Setup (705MHz) {34, 0x02}, {35, 0x71}, @@ -237,6 +242,80 @@ static const uint8_t m_si5351_regs_15to92_149to170[100][2] = { {64, 0x00}, {65, 0x00}}; +static const uint8_t m_si5351_regs_custom[51][2] = { + // Init + {3, 0xFF}, + {16, 0x4F}, /* CLK0 Control: 8mA drive, Multisynth 0 as CLK0 source, Clock + not inverted, Source = PLLA, Multisynth 0 in integer mode, + clock powered up */ + {17, 0x4F}, /* CLK1 Control: 8mA drive, Multisynth 1 as CLK1 source, Clock + not inverted, Source = PLLA, Multisynth 1 in integer mode, + clock powered up */ + {18, 0x6F}, /* CLK2 Control: 8mA drive, Multisynth 2 as CLK2 source, Clock + not inverted, Source = PLLB, Multisynth 2 in integer mode, + clock powered up */ + {19, 0x80}, /* CLK3 Control: Not used ... clock powered down */ + {20, 0x80}, /* CLK4 Control: Not used ... clock powered down */ + {21, 0x80}, /* CLK5 Control: Not used ... clock powered down */ + {22, 0x80}, /* CLK6 Control: Not used ... clock powered down */ + {23, 0x80}, /* CLK7 Control: Not used ... clock powered down */ + {24, 0x00}, /* Clock disable state 0..3 (low when disabled) */ + {25, 0x00}, /* Clock disable state 4..7 (low when disabled) */ + // PLL_A Setup (900MHz) (36 + 0/1) + // P1: 4096 => 0x01000 + // P2: 0 => 0x00000 + // P3: 1 => 0x00001 + {26, 0x00}, // D7 - D0: MSNA_P3 [15:8] + {27, 0x01}, // D7 - D0: MSNA_P3 [7:0] + {28, 0x00}, // D1 - D0: MSNA_P1 [17:16] + {29, 0x10}, // D7 - D0: MSNA_P1 [15:8] + {30, 0x00}, // D7 - D0: MSNA_P1 [7:0] + {31, 0x00}, // D7 - D4: MSNA_P3 [19:16], D3 - D0: MSNA_P2 [19:16] + {32, 0x00}, // D7 - D0: MSNA_P2 [15:8] + {33, 0x00}, // D7 - D0: MSNA_P2 [7:0] + // PLL_B Setup (375MHz) (15 + 0/1) + /* // P1: 1408 => 0x00580 */ + /* // P2: 0 => 0x00000 */ + /* // P3: 1 => 0x00001 */ + {34, 0x00}, // D7 - D0: MSNB_P3 [15:8] */ + {35, 0x01}, // D7 - D0: MSNB_P3 [7:0] */ + {36, 0x00}, // D1 - D0: MSNB_P1 [17:16] */ + {37, 0x05}, // D7 - D0: MSNB_P1 [15:8] */ + {38, 0x80}, // D7 - D0: MSNB_P1 [7:0] */ + {39, 0x00}, // D7 - D4: MSNB_P3 [19:16], D3 - D0: MSNA_P2 [19:16] */ + {40, 0x00}, // D7 - D0: MSNB_P2 [15:8] */ + {41, 0x00}, // D7 - D0: MSNB_P2 [7:0] */ + // Multisynth0 Setup (120MHz) + // P1: 1 + // P2: 0 + // P3: 1 + {42, 0x00}, // D7 - D0: MS0_P3 [15:8] + {43, 0x01}, // D7 - D0: MS0_P3 [7:0] + {44, 0x00}, // D6 - D4: R0_DIV [2:0], D3 - D2: MS0_DIVBY4 [1:0], D1 -D0: MS0_P1 [17:16] + {45, 0x01}, // D7 - D0: MS0_P1 [15:8] + {46, 0x01}, // D7 - D0: MS0_P1 [7:0] + {47, 0x00}, // D7 - D4: MS0_P3 [19:16], D3 - D0: MS0_P2 [19:16] + {48, 0x00}, // D7 - D0: MS0_P2 [15:8] + {49, 0x00}, // D7 - D0: MS0_P2 [7:0] + // Multisynth1 Setup (12MHz) + {50, 0x00}, + {51, 0x01}, + {52, 0x00}, + {53, 0x1C}, + {54, 0x00}, + {55, 0x00}, + {56, 0x00}, + {57, 0x00}, + // Multisynth2 Setup (13.56MHz) + {58, 0x00}, + {59, 0x01}, + {60, 0x00}, + {61, 0x18}, + {62, 0x00}, + {63, 0x00}, + {64, 0x00}, + {65, 0x00}}; + static void spi_init(void) { SPI_DDR |= (1 << SPI_SCK) | (1 << SPI_MOSI) | (1 << SPI_SS); SPI_PORT |= (1 << SPI_SS); @@ -878,9 +957,9 @@ int main(void) { (void) &twi_read_register; (void) &twi_write_register; - for (uint16_t i = 0; i < sizeof(m_si5351_regs_15to92_149to170) / 2; i++) - twi_write_register(SI5351_ADDRESS, m_si5351_regs_15to92_149to170[i][0], - m_si5351_regs_15to92_149to170[i][1]); + for (uint16_t i = 0; i < sizeof(m_si5351_regs_custom) / 2; i++) + twi_write_register(SI5351_ADDRESS, m_si5351_regs_custom[i][0], + m_si5351_regs_custom[i][1]); twi_write_register(SI5351_ADDRESS, SI5351_REGISTER_177_PLL_RESET, 0xAC); twi_write_register(SI5351_ADDRESS, SI5351_REGISTER_3_OUTPUT_ENABLE_CONTROL, 0x00);